The present invention relates, in general, to a single register control technique for a memory controller. More particularly, the present invention relates to a single register control technique for a memory controller in conjunction with a dynamic random access memory ("DRAM") array incorporating an onboard static RAM ("SRAM") cache which allows for readily implemented circuitry facilitating cache reads and page-mode writes.
The performance of computer central processing units ("CPU") has increased dramatically in recent years and has far exceeded that of any corresponding increase in the performance of main memory DRAM. In addition, the performance demands placed on main memory from computer input/output ("I/O") devices has also increased as well. As a consequence, DRAM main memory performance has been improved by utilizing faster SRAM cache memory to retain the most commonly accessed data. In some CPUs, this cache memory may be integrated directly with the processor chip in order to maximize the cache performance and system bandwidth. Nevertheless, sufficient SRAM cannot generally be integrated with the CPU chip for the possible range of applications, and ultimately it is the DRAM main memory access time and bandwidth which are the ultimate constraints in achieving maximum CPU performance.
On the other hand, overall computer I/O performance may also be improved by providing faster or "local" processor busses. In addition, where feasible, the I/O computation and local memory requirements of basic computer I/O devices may be distributed to the devices themselves in order to reduce the main memory bus bandwidth. Regardless of the techniques employed, the net result is generally more complicated and expensive hardware and the current trend involves locating I/O devices to the processor local bus for higher performance and overall lower systems cost.
In either instance, ever more rapidly increasing CPU and I/O performance point out the need for even higher bandwidth and faster access time DRAM main memory. Standard DRAM bandwidth may, to some extent, be improved by interleaving multiple memory banks and increasing bus widths. However, such approaches are ultimately only an attempt to work around the inherently slow access time provided by current DRAM technology and do not directly address the generally poor access times or inherent "wait" states required to access a new page of memory. Because of this, secondary external SRAM cache memory has been utilized to minimize the number of page misses experienced by the processor. However, such techniques tend to result in a more complex design as well as higher system cost and power requirements.
As a consequence, a number of specialty DRAM products have recently been introduced which obviate the need for external SRAM cache memory and DRAM interleaving. Among these devices are the Mitsubishi Cached DRAM ("CDRAM") and the proprietary Enhanced DRAM ("EDRAM.TM.") developed by Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, Colo. 80921, assignee of the present invention. The Ramtron EDRAM integrates an SRAM cache memory with a fast thirty five nanosecond access DRAM on a single chip. Among the benefits of this device are improved DRAM performance due to the fact that the current row of data being accessed from the memory array is held in a true SRAM cache memory which may be asynchronously accessed by the CPU in as little as fifteen nanoseconds. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array in as little as thirty-five nanoseconds over a 256 byte DRAM-to-cache memory bus. The EDRAM also utilizes an on-chip write posting register to perform write operations in fifteen nanoseconds and burst writes within a page are also performed at a similar rate of fifteen nanoseconds per word and an on-chip "hit"/"miss" comparator automatically maintains cache coherency.
Both the CDRAM and the EDRAM require specific controller designs to fully implement their features. In the former instance, the memory controller requires a cache controller with tag RAM and DRAM controller functions. In the latter instance, the controller may be implemented in a more straightforward manner due to the inherently less complex page cache algorithm employed. Nevertheless, a memory controller for either the CDRAM or the EDRAM which supports both cache reads as well as page-mode writes at high speed, has heretofore required both a last-row read register (to determine cache "hits") and a separate last-row written register (to facilitate page/mode "writes") requiring additional hardware in the memory controller design. The necessity of incorporating separate last-row read and last-row written registers adds to the overall cost of the memory controller to such an undesired extent that most designers and manufacturers will choose to omit the latter feature rather than incorporate the additional hardware necessary to implement it.